Envelope detectors are known in the art. Envelope detectors can be used to generate an output signal representing the envelope level or amplitude of a high frequency input signal. This can be used in many applications, such as demodulating an amplitude modulated input signal, detecting the strength of a received radio frequency (RF) signal, detecting the level of a generated RF signal for use in amplitude leveling loops, detecting the level of a generated RF signal for use in an amplitude feedback loop such as in a polar modulator, or for other suitable applications.
FIG. 1 is a schematic diagram of a prior art envelope detector 100. Envelope detector 100 comprises rectifying transistor 101, capacitor 102, resistor 103, holding capacitor 104, bias current source 105, optional DC offset replica circuit 106, and optional subtracting amplifier 107. Rectifying transistor 101 is configured to receive at a first terminal a bias voltage through resistor 103 and an input RF signal through capacitor 102. The first terminal of rectifying transistor 101 can be the gate if rectifying transistor 101 is a field-effect transistor (FET), the base if rectifying transistor 101 is a bipolar junction transistor (BJT), or other suitable control terminals for other devices.
A second terminal of rectifying transistor 101 is connected to holding capacitor 104 at an output node 108 and provided a bias current from bias current source 105. The second terminal of rectifying transistor 101 can be the source if rectifying transistor 101 is a FET, or the emitter if rectifying transistor 101 is a BJT. Holding capacitor 104 is selected such that the response time of the voltage at output node 108 is substantially slower than the period of frequency of the RF input. By using a nonlinear rectifying transistor 101, the average voltage at output node 108 can respond to the amplitude of the input RF signal.
Output node 108 can have a DC voltage even when the RF input amplitude is zero. For instance, if rectifying transistor 101 is a FET, the DC voltage at output node 108 can be approximately one threshold voltage below the bias voltage applied to the gate of rectifying transistor 101 when the RF input amplitude is zero. This DC offset can be detrimental if a small amplitude of the RF input is to be measured. Optional DC offset replica circuit 106, which can contain replicas of rectifying transistor 101 and bias current source 105, can be used to replicate this DC voltage. Optional subtracting amplifier 107 can then be used to remove this offset voltage from the output signal representing the detected envelope.
FIG. 2 is a diagram of curve 201 showing a typical response of a prior art envelope detector, such as envelope detector 100. Curve 201 depicts the voltage output, such as the output of subtracting amplifier 107, versus an RF input amplitude, such as the amplitude of the RF input signal coupled to rectifying transistor 101. This curve can typically be linear for a sufficiently large input amplitude, but can deviate from this linear response when the input amplitude is small. This nonlinearity can have an effect similar to an offset voltage, such that the extrapolated response of the high input amplitude range crosses the x axis at a non-zero point 202 while the actual response begins to curve. This effect can be caused when rectifying transistor 101 is not receiving a large enough signal amplitude for the transistor to operate as a nonlinear device, and can cause the average voltage output by the envelope detector to be nearly independent of the input RF signal amplitude until the amplitude reaches a sufficient level so that the rectifying device begins to behave in a nonlinear fashion.
There are at least two different sources of offset, as shown by curve 201. One is caused by the DC bias point of the detector output not typically being zero, so that even when there is no RF input, the voltage at 108 is nonzero. This offset can be corrected using a replica circuit to generate the same DC value using like circuitry and subtracting this off of the detected value.
Nevertheless, curve 201 will remain at zero even for a small nonzero input amplitude, due to the signal level being too small to activate the nonlinearity of transistor 101. The detector output DC does not change until the amplitude gets large enough so that transistor 101 becomes nonlinear and begins to re-bias the voltage 108 in response to changes in input amplitude.
This offset voltage effect can be detrimental when very small input signals must be detected. The offset voltage can also degrade performance of systems even when the input RF amplitude is typically high enough that the envelope detector is operating in the linear region, because the output in this region is proportional to the input amplitude minus the effective offset voltage. In systems such as polar feedback loops, it can be necessary that this offset voltage be nearly zero. An RF amplifier could be used to increase the amplitude of the RF input signal presented to the envelope detector in order to reduce this effect, but the application of an RF amplifier in this manner can cause other issues, such as saturation of the RF signal when higher amplitudes are present, and nonlinearity of the input to output response of the amplifier.